1. Field of the Invention
The present invention relates to a clamping circuit for a video receiving device and, more particularly, to an adaptive clamping circuit which adaptively changes an integral time constant to reproduce a reference signal interval for recovering a lost direct current signal resulting from transmission and reception of a video signal.
2. Brief Discussion of Related Art
A clamping circuit is generally used to convert a signal received through a capacitor into a signal of "0" level, e.g., a reference level. A diode and a resistance are connected in parallel with the capacitor. In this configuration, the conventional clamping circuit requires much time in which to reach an initial equilibrium state and the clamping circuit continues to operate unstably after reaching a steady state due to a time constant set equal to a predetermined value.
The fact that a clamping circuit has a large adaption time in the initial state causes a video signal to be produced in an unsteady state and causes an audio signal to be produced with a high noise content for a long period, e.g., until the steady state is reached after application of supply power. In an effort to minimize these problems, a mute operation is performed on both of the video and audio signals. Furthermore, instability during the operation of the clamping circuit in the steady state results in a level change in the video signal, which, it will noted, produces a flicker phenomenon, thereby generating errors in, e.g., the digital audio signal processing of a Multiple Sub-Nyquist Sampling Encoding (MUSE) broadcasting system. In an effort to solves this latter problem, the mute operation also must be performed for video and audio signals.
FIG. 1 shows a schematic diagram of a conventional circuit briefly described above. An analog signal input to an input terminal Ii is buffered in a buffer 101, the direct current component is cut off by a capacitor Cc and, then, the alternating current component is digitized in A/D converter 102. Thus, the signal which passes the capacitor Cc is converted into a digital signal by the A/D converter 102, which digital signal is input to a digital signal processing circuit (not shown), but only the most significant bit (MSB) and an additional bit M-1 of the digital signals are provided to a code converter 103. The MSB signal is also input to the negative terminal (-) of an operational amplifier OP1 through switches SW1, SW2 for performing a clamping action. It will be noted that the MSB signal is used for performing the clamping action because the MSB signal corresponds to a top level for all input signals.
FIG. 2 illustrates the preferred configuration for code converter 103 of FIG. 1, wherein MSB and M-1 signals are used in generating signal Q1 via an exclusive OR gate (XOR), which signal is inverted with respect to bits of a signal Q2 by an inverter N1 as indicated in the following Table 1.
TABLE 1 ______________________________________ MSB M-1 Q1 Q2 ______________________________________ 1 1 1 0 1 0 0 1 0 1 0 1 0 0 1 0 ______________________________________
The output MSB and M-1 signals are input to exclusive OR gate XOR. When MSB and M-1 input signals are in the same state, the output of exclusive OR gate XOR goes "low" and, when MSB and M-1 input signals are in different states, the output of exclusive OR gate XOR goes "high". When MSB and M-1 signals are all "1", it suggests a very high input level, and, in contrast, when MSB and M-1 signals are both "0", it suggests a very low input level. It will be noted from this discussion that certain actions must be taken for rapidly varying levels of input signals represented by logic values of Q1 and Q2 of the reference level.
More specifically, in FIG. 1, the outputs Q1, Q2 of code converter 103 are input to one input of AND gates 104, 105, respectively, while the other input of AND gates 104, 105 is connected to a vertical clamp terminal VC. As shown by reference numeral 301 in FIG. 3, when the input level of the vertical clamp terminal VC is "high", the AND gates 104, 105 turn on/off switches SW1, SW2 according to the output of the code converter 103, permitting the levels of input signals to be adjusted. When switches SW1, SW2 are turned on, the MSB signal output from the A/D converter 102 is filtered by an RC filter comprising resistances R1, R3 and capacitors C1, C2. This filtered signal is then integrated in an integrating circuit 106 and, thereafter, converted into a direct current (DC) level. Then, the output of an operational amplifier OP1 us used to charge a capacitor C.sub.ch.
The current used in charging the capacitor C.sub.ch is switched on/off by a horizontal clamping pulse, so as to set the direct current voltage during a horizontal duration HD portion of every line in response to a signal provided to a horizontal clamp terminal HC, as shown by reference number 302 of FIG. 3. Here, clamp levels are all within a locked 128/256 range, e.g., the neutral level of the MUSE input signal, which is set in the transmitting side.
During operation, the clamp signal is quantized as a low level corresponding to an initial state and a high level corresponding to a fully charged state of the capacitor C.sub.ch ; thus, the input codes of the code converter 103 all start at a "low" level (0). At this time, the MSB signal is in "low" state, meaning that the signal input to A/D converter 102 is a "low" level signal. As indicated in Table 1, the MSB signal is sequentially applied to resistances R1, R2, capacitors C1, C2, and negative input terminal of the operational amplifier OP1 via switches SW1, SW2 to thereby raise the charge voltage of the capacitor C.sub.ch, whereby the signal level of direct current component applied to the A/D converter 102 is raised. At this time, switches SW1, SW2 are turned on respectively depending on the level of a clamping signal. This is because the RC time constants associated with resistances R1, R3, and capacitors C1, C2, respectively, are different from each other. During operation, switch SW1 operates at a high speed, whereas switch SW2 is a relatively low speed switch.
In performing a clamping operation, the voltage range of the clamp becomes ##EQU1## This voltage range makes it difficult to adjust the clamp level according to the results of the detection, and, hence, to vary the input signal levels. This is because the voltage range is too broad to stabilize the clamp level. In order to increase the clamping speed, switching speeds of switches SW1, SW2 must be increased. However, in order to stabilize the clamp level, switching speeds of switches SW1, SW2 must be reduced. It will be noted that it is not possible to satisfy all requirements regarding switching speed.